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XMEGA A [MANUAL]
8077I–AVR–11/2012
For BSEL=0, all baud rates must be achieved by changing BSEL instead of setting BSCALE:
BSEL = (2 BSCALE-1)
21.3.2 External Clock
External clock (XCK) is used in synchronous slave mode operation. The XCK clock input is sampled on the peripheral
clock frequency (fPER), and the maximum XCK clock frequency (fXCK)is limited by the following:
For each high and low period, XCK clock cycles must be sampled twice by the peripheral clock. If the XCK clock has
jitter, or if the high/low period duty cycle is not 50/50, the maximum XCK clock speed must be reduced or the peripheral
clock must be increased accordingly.
21.3.3 Double Speed Operation
Double speed operation allows for higher baud rates under asynchronous operation with lower peripheral clock
frequencies. When this is enabled, the baud rate for a given asynchronous baud rate setting shown in Table 21-1 on
page 233 will be doubled. In this mode, the receiver will use half the number of samples (reduced from 16 to 8) for data
sampling and clock recovery. Due to the reduced sampling, a more accurate baud rate setting and peripheral clock are
required. See “Asynchronous Data Reception” on page 238 for more details.
21.3.4 Synchronous Clock Operation
When synchronous mode is used, the XCK pin controls whether the transmission clock is input (slave mode) or output
(master mode). The corresponding port pin must be set to output for master mode or to input for slave mode. The normal
port operation of the XCK pin will be overridden. The dependency between the clock edges and data sampling or data
change is the same. Data input (on RxD) is sampled at the XCK clock edge which is opposite the edge where data output
(TxD) is changed.
BSCALE
BSEL
BSCALE
BSEL
1
0
0
1
2
0
0
3
0
0
7
4
0
0
15
5
0
0
31
6
0
0
63
7
0
0
127
f
XCK
f
PER
4
-----------
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